基本信息

张岩龙，副教授，博士生导师

联系方式

Email：yanlong.zhang@xjtu.edu.cn

地址：陕西省西安市咸宁西路28号西一楼

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我的新闻

个人简介

张岩龙，博士，分别于2011年、2018年在西安电子科技大学获得微电子学专业学士学位和微电子学与固体电子学博士学位。研究生期间获得国家奖学金，主要从事超宽带射频集成电路设计的相关研究工作。2015年10至2017年11月，作为国家公派联合培养博士研究生赴美国德州大学奥斯汀分校（UT Austin）留学，主要从事低噪声锁相环设计和时间域数据转换器设计的相关研究工作。2018年7月入职微电子学院。

研究领域

1)     时间域模拟/混合信号集成电路（Time-domain analog/mixed-signal ICs）

2)     高速、宽带射频集成电路（High-speed and wideband RFICs）

3)     毫米波集成电路（Millimeter-wave ICs）

4)     模拟/混合信号集成电路自动化设计技术（AMS IC design automation）

科研项目

主持项目：

1) 国家自然科学基金青年科学基金项目

2) 陕西省青年人才托举计划项目

3) 中央高校基本科研业务费项目

 

参与项目：

1) 国家自然科学基金面上项目

2) 国家自然科学基金青年科学基金项目

科研成果与获奖情况

1.     发表论文

期刊论文：

[1] Xiaochuan Zhou, Xiaoyan Gui, Marjan Gusev, Nevena Ackovska, Yanlong Zhang, Li Geng, "A 12-Bit 20-kS/s 640-nW SAR ADC With a VCDL-Based Open-Loop Time-Domain Comparator," IEEE Transactions on Circuits and Systems II: Express Briefs, vol. 69, no. 2, pp. 359-363, Feb. 2022.

[2]  Xiaoyan Gui, Renjie Tang, Yanlong Zhang, Dan Li, and Li Geng, “A Voltage-Controlled Ring Oscillator With VCO-Gain Variation Compensation,” IEEE Microwave and Wireless Components Letters, vol. 30, no. 3, pp. 288–291, Mar. 2020.

[3]  Yanlong Zhang, Arindam Sanyal, Xueyi Yu, Xing Quang, Kailin Wen, Xiyuan Tang, Gang Jin, Li Geng, and Nan Sun, “A Fractional-N PLL With Space-Time Averaging for Quantization Noise Reduction,” IEEE Journal of Solid-State Circuits, vol. 55, no. 3, pp. 602–614, Mar. 2020. (CICC invited submission)

[4]  Arindam Sanyal, Xueyi Yu, Yanlong Zhang, and Nan Sun, “Fractional-N PLL with multi-element fractional divider for noise reduction,” Electronics Letters, vol. 52, no. 10, pp. 809–810, May 2016.

[5]  Xing Quan, Yiqi Zhuang, Zhenrong Li, Yanlong Zhang, Kai Jing. “A 2–22GHz low-imbalanced active balun in 0.18μm SiGe BiCMOS technology”. AEU-International Journal of Electronics and Communications, vol. 70, no. 10, pp. 1367–1373, Oct. 2016.

[6]  Xing Quan, Yiqi Zhuang, Zhenrong Li, Yanlong Zhang, Kai Jing, and Jinsong Zhan. “Current generator for 6-bit active phase shifter”. Electronics Letters, vol. 51, no. 15, pp. 1175–1177, Jul. 2015.

[7]  张岩龙, 庄奕琪, 李振荣, 任小娇, 齐增卫, 杜永乾, 李红云. “一种5～20GHz低插损低相位误差的CMOS衰减器”. 西安电子科技大学学报, 2015, 42(2): 935–939.

[8]  Yanlong Zhang, Yiqi Zhuang, Zhenrong Li, Hongyun Li, Xing Quan, Bo Wang, and Xiaojiao Ren. “A CMOS semi-distributed step attenuator with low insertion loss and low phase distortion”. IEICE Electronics Express, vol. 11, no. 12, pp. 1–5, Jun. 2014.

[9]  Yanlong Zhang, Yiqi Zhuang, Zhenrong Li, Xing Quan, and Xiaojiao Ren. “A broadband 5-bit CMOS step attenuator in small area with low insertion loss”. IEICE Electronics Express, vol. 11, no. 9, pp. 1–5, May 2014.

[10]  Yanlong Zhang, Yiqi Zhuang, Zhenrong Li, Xiaojiao Ren, Bo Wang, Kai Jing, and Zengwei Qi. “A 5-bit lumped 0.18-μm CMOS step attenuator with low insertion loss and low phase distortion in 3–22 GHz applications”. Microelectronics Journal, vol. 45, no. 4, pp. 468–476, Apr. 2014. 

[11]  Kai Jing, Yiqi Zhuang, Zhenrong Li, Yongqian Du, Yanlong Zhang. A SiGe HBT low noise amplifier using on-chip notch filter for K band wireless communication, Microelectronics Journal, vol. 45 no. 6, pp. 683–689, Jun. 2014.

 

会议论文：

[1] Marjan Gusev, Nevena Ackovska, Vladimir Zdraveski, Emil Stankov, Mile Jovanov, Martin Dinev, Dejan Spasov, Xiaoyan Gui, Yanlong Zhang, Li Geng, Xiaochuan Zhou, "Review of Drowsiness Detection Machine-Learning Methods Applicable for Non-Invasive Brain-Computer Interfaces," in 29th Telecommunications Forum (TELFOR), Nov. 2021, pp. 1-4.

[2] Shengyu Liang, Youze Xin, Chenglong Liang, Bin Zhang, Yanlong Zhang, Xiaoli Wang, Li Geng, “A 0.025% DC Current Mismatch Charge Pump for PLL Applications,” in Proc. IEEE International Midwest Symposium on Circuits and Systems (MWSCAS), Apr. 2021, pp. 700–703.

[3] Liheng Liu, Yanlong Zhang, Li Dong, Youze Xin, Shengwei Gao, Li Geng, “A Power Efficient ECG Front-End with Input-Adaptive Gain Reaching 67.6-dB Dynamic Range,” in Proc. IEEE Asian Solid-State Circuits Conference (A-SSCC), Apr.2020, pp. 1–4.

[4]  Yanlong Zhang, Arindam Sanyal, Xing Quan, Kailin Wen, Xiyuan Tang, Gang Jin, Li Geng, and Nan Sun, “A 2.4-GHz ΔΣ fractional-N synthesizer with space-time averaging for noise reduction,” in Proc. IEEE Custom Integrated Circuits Conference (CICC), Apr. 2019, pp. 1–4.

 

2.     出版著作

[1]  贾新章, 游海龙, 高海霞, 张岩龙. 电子线路CAD 与优化设计——基于Cadence/PSpice, 北京: 电子工业出版社, 2014.

 

3.     邀请报告

[1]  2020.12, "Noise Reduction for Fractional-N Phase-Locked Loops", IEEE 2nd International Conference on Circuits and Systems（IEEE ICCS 2020）.

[2]  2020.06, "A Fractional-N PLL With Space–Time Averaging for Quantization Noise Reduction", 第二届华人芯片设计技术研讨会（ICAC 2020）.

指导研究生和本科生情况

2018年至今，共指导研究生5名，指导10名本科生完成毕业设计。

 

本团队主要从事射频、模拟/混合信号集成电路与系统的前沿技术与实践应用的相关研究，欢迎有志从事集成电路设计前沿技术研究的同学加入我们！